TSMC, the world’s leading semiconductor foundry, announced a significant breakthrough in AI technology innovations at its 2024 North America Technology Symposium in Santa Clara, California, marking the event’s 30th anniversary. The symposium showcased TSMC’s latest advancements in semiconductor processes, advanced packaging, and 3D IC technologies, which will catalyze the next wave of AI applications across various sectors.

Among the key highlights, TSMC introduced the TSMC A16 Technology and System-on-Wafer (TSMC-SoW™) technology, both set to enhance computing power and efficiency, particularly for use in large-scale AI infrastructure, such as hyperscaler datacenters.

The newly unveiled TSMC A16 Technology features cutting-edge nanosheet transistors along with a novel Super Power Rail architecture. Scheduled for production in 2026, this innovation promises up to 10% speed enhancement and 20% power reduction at the same speed, coupled with an increase in chip logic density, making it particularly suited for high-performance computing (HPC) products that require complex signal routing and dense power delivery networks.

Moreover, the introduction of TSMC NanoFlex™ for N2 technology represents a pioneering step in design-technology co-optimization. This will allow designers to selectively integrate short and tall cells within their chip designs to finely balance power, performance, and area efficiencies according to specific product requirements.

TSMC also announced the N4C Technology, an extension of the N4P process, which will commence volume production in 2025. N4C aims to make TSMC’s advanced technology more accessible, especially for value-tier products, promising up to 8.5% reduction in die cost with minimal adoption effort.

Notably, the symposium spotlighted the System-on-Wafer (TSMC-SoW™) technology, a radical new development in wafer-level system integration. Set to be ready in 2027, this technology involves incorporating multiple dies on a single 300mm wafer, utilizing integrated fan-out and chip-on-wafer advances to significantly enhance computing power while reducing data center space requirements.

In parallel, TSMC is progressing in the field of silicon photonics through its Compact Universal Photonic Engine (COUPE™), which is set to disrupt data communication technology by enabling more efficient data transfer. Scheduled for qualification in 2025, COUPE will be integrated into the CoWoS packaging technology as co-packaged optics by 2026.

The symposium also underscored ongoing developments in advanced packaging solutions for automotive applications, highlighting TSMC’s commitment to supporting the automotive industry’s evolving needs for high-performance computing, crucial for the next generation of advanced driver assistance systems and vehicle control computers.

From its inaugural symposium drawing less than 100 attendees to hosting over 2,000 participants this year, TSMC’s Silicon Valley event not only reflects the company’s growth but also its pivotal role in shaping future technology landscapes. As TSMC continues to expand its global footprint and technology leadership, its innovations are set to play a crucial role in powering new levels of connectivity, computational efficiency, and intelligence in devices across the spectrum, from mobile devices to expansive data centers.